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1/17 march 2002 m27v160 16 mbit (2mb x8 or 1mb x16) low voltage uv eprom and otp eprom n 3v to 3.6v low voltage in read operation n access time: 100ns n byte-wide or word-wide configurable n 16 mbit mask rom replacement n low power consumption C active current 30ma at 8mhz C standby current 60a n programming voltage: 12.5v 0.25v n programming time: 50s/word n electronic signature C manufacturer code: 20h C device code: b1h description the m27v160 is a low voltage 16 mbit eprom of- fered in the two ranges uv (ultra violet erase) and otp (one time programmable). it is ideally suited for microprocessor systems requiring large data or program storage. it is organised as either 2 mbit words of 8 bit or 1 mbit words of 16 bit. the pin-out is compatible with a 16 mbit mask rom. the m27v160 operates in the read mode with a supply voltage as low as 3v. the decrease in op- erating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. the fdip42w (window ceramic frit-seal package) has a transparent lid which allows the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. a new pattern can then be written rapidly to the device by following the programming proce- dure. for applications where the content is programmed only one time and erasure is not required, the m27v160 is offered in pdip42, sdip42, plcc44 and so44 packages. 1 42 1 42 fdip42w (f) pdip42 (b) so44 (m) plcc44 (k) sdip42 (s) 1 42 figure 1. logic diagram ai01898 20 a0-a19 bytev pp q0-q14 v cc m27v160 g e v ss 15 q15aC1
m27v160 2/17 figure 2b. so connections g q0 q8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 q7 a12 a16 bytev pp q15a-1 q5 q2 q3 v cc q11 q4 q14 a9 a19 a18 a4 nc nc a7 ai01900 m27v160 8 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 q1 q9 a6 a5 q6 q13 44 39 38 37 36 35 34 33 a11 a10 q10 21 q12 40 43 1 42 41 a17 a8 figure 2a. dip connections g q0 q8 a3 a0 e v ss a2 a1 a13 v ss a14 a15 q7 a12 a16 bytev pp q15a-1 q5 q2 q3 v cc q11 q4 q14 a9 a8 a17 a4 a18 a19 a7 ai01899 m27v160 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 20 19 18 17 q1 q9 a6 a5 q6 q13 42 39 38 37 36 35 34 33 a11 a10 q10 21 q12 40 41 table 1. signal names a0-a19 address inputs q0-q7 data outputs q8-q14 data outputs q15aC1 data output / address input e chip enable g output enable byte v pp byte mode / program supply v cc supply voltage v ss ground nc not connected internally figure 2c. plcc connections ai04829 a11 a14 q7 q5 23 q0 q8 q1 q9 q2 nc q12 a4 a0 e v ss a3 a2 12 a10 a16 1 a7 bytev pp a13 a5 q6 44 v ss a9 m27v160 a6 a12 q13 v ss q14 34 q10 a1 a15 q15aC1 g q3 q11 v cc q4 a18 a17 a8 a19
3/17 m27v160 table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum dc voltage on input or output is C0.5v with possible undershoot to C2.0v for a period less than 20ns. maximum dc voltage on output is v cc +0.5vwithpossibleovershoottov cc +2v for a period less than 20ns. 3. depends on range. table 3. operating modes note: x = v ih or v il ,v id = 12v 0.5v. table 4. electronic signature symbol parameter value unit t a ambient operating temperature (3) C40 to 125 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltage (except a9) C2 to 7 v v cc supply voltage C2 to 7 v v a9 (2) a9 voltage C2 to 13.5 v v pp program supply voltage C2 to 14 v mode e g byte v pp a9 q15aC1 q14-q8 q7-q0 read word-wide v il v il v ih x data out data out data out read byte-wide upper v il v il v il x v ih hi-z data out read byte-wide lower v il v il v il x v il hi-z data out output disable v il v ih x x hi-z hi-z hi-z program v il pulse v ih v pp x data in data in data in verify v ih v il v pp x data out data out data out program inhibit v ih v ih v pp x hi-z hi-z hi-z standby v ih x x x hi-z hi-z hi-z electronic signature v il v il v ih v id code codes codes identifier a0 q15 and q7 q14 and q6 q13 and q5 q12 and q4 q11 and q3 q10 and q2 q9 and q1 q8 and q0 hex data manufacturers code v il 00100000 20h device code v ih 10110001 b1h
m27v160 4/17 device operation the operating modes of the m27v160 are listed in the operating modes table. a single power supply is required in the read mode. all inputs are ttl compatible except for v pp and 12v on a9 for the electronic signature. read mode the m27v160 has two organisations, word-wide and byte-wide. the organisation is selected by the signal level on the byte v pp pin. when byte v pp is at v ih the word-wide organisation is selected and the q15aC1 pin is used for q15 data output. when the byte v pp pin is at v il the byte-wide or- ganisation is selected and the q15aC1 pin is used for the address input aC1. when the memory is logically regarded as 16 bit wide, but read in the byte-wide organisation, then with aC1 at v il the lower 8 bits of the 16 bit data are selected and with aC1 at v ih the upper 8 bits of the 16 bit data are selected. the m27v160 has two control functions, both of which must be logically active in order to obtain data at the outputs. in addition the word-wide or byte- wide organisation must be selected. chip enable (e ) is the power control and should be used for device selection. output enable (g )isthe output control and should be used to gate data to the output pins independent of device selection. assuming that the addresses are stable, the ad- dress access time (t avqv ) is equal to the delay from e to output (t elqv ). data is available at the output after a delay of t glqv from the falling edge of g , assuming that e has been low and the ad- dresses have been stable for at least t avqv -t glqv . table 5. ac measurement conditions high speed standard input rise and fall times 10ns 20ns input pulse voltages 0 to 3v 0.4v to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v figure 3. ac testing input output waveform ai01822 3v high speed 0v 1.5v 2.4v standard 0.4v 2.0v 0.8v figure 4. ac testing load circuit ai01823b 1.3v out c l c l = 30pf for high speed c l = 100pf for standard c l includes jig capacitance 3.3k w 1n914 device under test table 6. capacitance (1) (t a =25c,f=1mhz) note: 1. sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance (except byte v pp )v in =0v 10 pf input capacitance (byte v pp )v in =0v 120 pf c out output capacitance v out =0v 12 pf
5/17 m27v160 table 7. read mode dc characteristics (1) (t a = 0 to 70c or C40 to 85c; v cc =3.3v10%;v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. maximum dc voltage on output is v cc +0.5v. symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 10 a i cc supply current e =v il ,g =v il ,i out = 0ma, f = 8mhz, v cc 3.6v 30 ma e =v il ,g =v il ,i out = 0ma, f = 5mhz, v cc 3.6v 20 ma i cc1 supply current (standby) ttl e =v ih 1ma i cc2 supply current (standby) cmos e >v cc C 0.2v, v cc 3.6v 60 a i pp program current v pp =v cc 10 a v il input low voltage C0.3 0.2v cc v v ih (2) input high voltage 0.7v cc v cc +1 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C400a 2.4 v standby mode the m27v160 has a standby mode which reduces the active current from 20ma to 20a with low volt- age operation v cc 3.6v, see read mode dc characteristics table for details.the m27v160 is placed in the standby mode by applying a cmos high signal to the e input. when in the standby mode, the outputs are in a high impedance state, independent of the g input. two line output control because eproms are usually used in larger memory arrays, this product features a 2 line con- trol function which accommodates the use of mul- tiple memory connection. the two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. for the most efficient use of these two control lines, e should be decoded and used as the prima- ry device selecting function, while g should be made a common connection to all devices in the array and connected to the read line from the system control bus. this ensures that all deselect- ed memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. system considerations the power switching characteristics of advanced cmos eproms require careful decoupling of the supplies to the devices. the supply current i cc has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of e . the magnitude of the transient current peaks is dependent on the ca- pacitive and inductive loading of the device out- puts. the associated transient voltage peaks can be suppressed by complying with the two line out- put control and by properly selected decoupling capacitors. it is recommended that a 0.1f ceram- ic capacitor is used on every device between v cc and v ss . this should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. in addition, a 4.7f electrolytic capacitor should be used be- tween v cc and v ss for every eight devices. this capacitor should be mounted near the power sup- ply connection point. the purpose of this capacitor is to overcome the voltage drop caused by the in- ductive effects of pcb traces.
m27v160 6/17 figure 5. word-wide read mode ac waveforms note: byte v pp =v ih . ai00741b taxqx tehqz a0-a19 e g q0-q15 tavqv tghqz tglqv telqv valid hi-z valid table 8. read mode ac characteristics (1) (t a = 0 to 70c or C40 to 85c; v cc =3.3v10%;v pp =v cc ) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp 2. sampled only, not 100% tested. 3. speed obtained with high speed measurement conditions. symbol alt parameter test condition m27v160 unit -100 (3) -120 -150 min max min max min max t avqv t acc address valid to output valid e =v il ,g =v il 100 120 150 ns t bhqv t st byte high to output valid e =v il ,g =v il 100 120 150 ns t elqv t ce chip enable low to output valid g =v il 100 120 150 ns t glqv t oe output enable low to output valid e =v il 50 60 60 ns t blqz (2) t std byte low to output hi-z e =v il ,g =v il 45 50 50 ns t ehqz (2) t df chip enable high to output hi-z g =v il 045050050ns t ghqz (2) t df output enable high to output hi-z e =v il 045050050ns t axqx t oh address transition to output transition e =v il ,g =v il 555ns t blqx t oh byte low to output transition e =v il ,g =v il 555ns
7/17 m27v160 figure 6. byte-wide read mode ac waveforms note: byte v pp =v il . figure 7. byte transition ac waveforms note: chip enable (e ) and output enable (g )=v il . ai00742b taxqx tehqz aC1,a0-a19 e g q0-q7 tavqv tghqz tglqv telqv valid hi-z valid ai00743c taxqx tbhqv a0-a19 bytev pp tavqv tblqx tblqz valid hi-z aC1 data out data out valid q0-q7 q8-q15
m27v160 8/17 table 9. programming mode dc characteristics (1) (t a =25c;v cc = 6.25v 0.25v; v pp = 12.5v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . table 10. programming mode ac characteristics (1) (t a =25c;v cc = 6.25v 0.25v; v pp = 12.5v 0.25v) note: 1. v cc must be applied simultaneously with or before v pp and removed simultaneously or after v pp . 2. sampled only, not 100% tested. symbol parameter test condition min max unit i li input leakage current 0 v in v cc 1 m a i cc supply current 50 ma i pp program current e =v il 50 ma v il input low voltage C0.3 0.8 v v ih input high voltage 2.4 v cc +0.5 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage ttl i oh = C2.5ma 3.6 v v id a9 voltage 11.5 12.5 v symbol alt parameter test condition min max unit t avel t as address valid to chip enable low 2 s t qvel t ds input valid to chip enable low 2 s t vphav t vps v pp high to address valid 2s t vchav t vcs v cc high to address valid 2s t eleh t pw chip enable program pulse width 45 55 s t ehqx t dh chip enable high to input transition 2 s t qxgl t oes input transition to output enable low 2 s t glqv t oe output enable low to output valid 120 ns t ghqz (2) t dfp output enable high to output hi-z 0 130 ns t ghax t ah output enable high to address transition 0ns programming the m27v160 has been designed to be fully com- patible with the m27c160. as a result the m27v160 can be programmed as the m27c160 on the same programming equipments applying 12.75v on v pp and 6.25v on v cc by the use of the same presto iii algorithm. when delivered (and after each erasure for uv eprom), all bits of the m27v160 are in the '1' state. data is introduced by selectively programming '0's to the desired bit lo- cations. although only '0's will be programmed, both '1's and '0's can be present in the data word. the only way to change a '0' to a '1' is by die expo- sure to ultraviolet light (uv eprom). the m27v160 is in the programming mode when v pp input is at 12.5v, g is at v ih and e ispulsedtov il . the data to be programmed is applied to 16 bits in parallel to the data output pins. the levels required for the address and data inputs are ttl. v cc is specifiedtobe6.25v0.25v.
9/17 m27v160 presto iii programming algorithm the presto iii programming algorithm allows the whole array to be programed with a guaran- teed margin in a typical time of 52.5 seconds. pro- gramming with presto iii consists of applying a sequence of 50s program pulses to each word until a correct verify occurs (see figure 9). during programing and verify operation a mar- gin mode circuit is automatically activated to guarantee that each cell is programed with enough margin. no overprogram pulse is applied since the verify in margin mode at v cc much higher than 3.6v provides the necessary margin to each pro- grammed cell. program inhibit programming of multiple m27v160s in parallel with different data is also easily accomplished. ex- cept for e , all like inputs including g of the parallel m27v160 may be common. a ttl low level pulse applied to a m27v160's e input and v pp at 12.5v, will program that m27v160. a high level e input in- hibits the other m27v160s from being pro- grammed. program verify a verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. the verify is accomplished with e at v ih and g at v il ,v pp at 12.5v and v cc at 6.25v. figure 8. programming and verify modes ac waveforms tavel valid ai00744 a0-a19 q0-q15 bytev pp v cc g data in data out e tqvel tvphav tvchav tehqx teleh tglqv tqxgl tghqz tghax program verify figure 9. programming flowchart ai00901b n = 0 last addr verify e = 50 m s pulse ++n = 25 ++ addr v cc = 6.25v, v pp = 12.5v fail check all words bytev pp =v ih 1st: v cc = 5v 2nd: v cc = 3v yes no yes no yes no
m27v160 10/17 on-board programming the m27v160 can be directly programmed in the application circuit. see the relevant application note an620. electronic signature the electronic signature (es) mode allows the reading out of a binary code from an eprom that will identify its manufacturer and type. this mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the es mode is functional in the 25c 5c am- bient temperature range that is required when pro- gramming the m27v160. to activate the es mode, the programming equipment must force 11.5v to 12.5v on address line a9 of the m27v160, with v pp =v cc =5v. two identifier bytes may then be sequenced from the device outputs by toggling address line a0 from v il to v ih . all other address lines must be held at v il during electronic signature mode. byte 0 (a0 = v il ) represents the manufacturer code and byte 1 (a0 = v ih ) the device identifier code. for the stmicroelectronics m27v160, these two identifier bytes are given in table 4 and can be read-out on outputs q7 to q0. note that the m27v160 and m27c160 have the same identifier bytes. erasure operation (applies to uv eprom) the erasure characteristics of the m27v160 is such that erasure begins when the cells are ex- posed to light with wavelengths shorter than ap- proximately 4000 ?. it should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 ? range. research shows that constant exposure to room level fluo- rescent lighting could erase a typical m27v160 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. if the m27v160 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the m27v160 window to prevent unintentional era- sure. the recommended erasure procedure for m27v160 is exposure to short wave ultraviolet light which has a wavelength of 2537 ?. the inte- grated dose (i.e. uv intensity x exposure time) for erasure should be a minimum of 30 w-sec/cm 2 . the erasure time with this dosage is approximate- ly 30 to 40 minutes using an ultraviolet lamp with 12000 w/cm 2 power rating. the m27v160 should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. some lamps have a filter on their tubes which should be removed before erasure.
11/17 m27v160 table 11. ordering information scheme note: 1. high speed, see ac characteristics section for further information. 2. packages option available on request. please contact stmicroelectronics local sales office. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the stmicroelectronics sales office nearest to you. table 12. revision history example: m27v160 -100 x m 1 tr device type m27 supply voltage v = 3v to 3.6v device function 160 = 16 mbit (2mb x 8 or 1mb x 16) speed -100 (1) =100ns -120 = 120 ns -150 = 150 ns v cc tolerance blank = 3.3v 10% x=3.3v5% package f = fdip42w (2) b = pdip42 s = sdip42 k = plcc44 m = so44 (2) temperature range 1 = 0 to 70 c 6 = C40 to 85 c options tr = tape & reel packing date revision details march 2000 first issue 23-apr-2001 plcc44 package added 19-jul-2001 sdip42 package added 21-mar-2002 so44 package mechanical and data clarified
m27v160 12/17 table 13. fdip42w - 42 pin ceramic frit-seal dip, with window, package mechanical data symb mm inches typ min max typ min max a C 5.72 C 0.225 a1 0.51 1.40 0.020 0.055 a2 3.91 4.57 0.154 0.180 a3 3.89 4.50 0.153 0.177 b 0.41 0.56 0.016 0.022 b1 1.45 C C 0.057 C C c 0.23 0.30 0.009 0.012 d 54.41 54.86 2.142 2.160 d2 50.80 C C 2.000 C C e 15.24 C C 0.600 C C e1 14.50 14.90 0.571 0.587 e 2.54 C C 0.100 C C ea 14.99 C C 0.590 C C eb 16.18 18.03 0.637 0.710 l 3.18 4.10 0.125 0.161 s 1.52 2.49 0.060 0.098 k 9.40 C C 0.370 C C k1 11.43 C C 0.450 C C a 4 11 4 11 n42 42 figure 10. fdip42w - 42 pin ceramic frit-seal dip, with window, package outline drawing is not to scale. fdipw-b a3 a1 a l b1 b e1 d s e1 e n 1 c ea d2 k k1 a eb a2
13/17 m27v160 table 14. pdip42 - 42 pin plastic dip, 600 mils width, package mechanical data symb mm inches typ min max typ min max a C 5.08 C 0.200 a1 0.25 C 0.010 C a2 3.56 4.06 0.140 0.160 b 0.38 0.53 0.015 0.021 b1 1.27 1.65 0.050 0.065 c 0.20 0.36 0.008 0.014 d 52.20 52.71 2.055 2.075 d2 50.80 C C 2.000 C C e 15.24 C C 0.600 C C e1 13.59 13.84 0.535 0.545 e1 2.54 C C 0.100 C C ea 14.99 C C 0.590 C C eb 15.24 17.78 0.600 0.700 l 3.18 3.43 0.125 0.135 s 0.86 1.37 0.034 0.054 a 0 10 0 10 n42 42 figure 11. pdip42 - 42 pin plastic dip, 600 mils width, package outline drawing is not to scale. pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
m27v160 14/17 table 15. sdip42 - 42 pin shrink plastic dip, 600 mils width, package mechanical data symbol millimeters inches typ min max typ min max a 5.08 0.200 a1 0.51 0.020 a2 3.81 3.05 4.57 0.150 0.120 0.180 b 0.46 0.38 0.56 0.018 0.015 0.022 b2 1.02 0.89 1.14 0.040 0.035 0.045 c 0.25 0.23 0.38 0.010 0.009 0.015 d 36.83 36.58 37.08 1.450 1.440 1.460 e 1.78 C C 0.070 C C e 15.24 16.00 0.600 0.630 e1 13.72 12.70 14.48 0.540 0.500 0.570 ea 15.24 C C 0.600 C C eb 18.54 0.730 l 3.30 2.54 3.56 0.130 0.100 0.140 s 0.64 0.025 n42 42 figure 12. sdip42 - 42 pin shrink plastic dip, 600 mils width, package outline drawing is not to scale. sdip a2 a1 a l b2 b e d s e1 e n 1 c ea eb d2
15/17 m27v160 table 16. plcc44 - 44 lead plastic leaded chip carrier, package mechanical data symbol mm inches typ min max typ min max a 4.20 4.70 0.165 0.185 a1 2.29 3.04 0.090 0.120 a2 C 0.51 C 0.020 b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 d 17.40 17.65 0.685 0.695 d1 16.51 16.66 0.650 0.656 d2 14.99 16.00 0.590 0.630 e 17.40 17.65 0.685 0.695 e1 16.51 16.66 0.650 0.656 e2 14.99 16.00 0.590 0.630 e 1.27 C C 0.050 C C f 0.00 0.25 0.000 0.010 r 0.89 C C 0.035 C C n44 44 cp 0.10 0.004 figure 13. plcc44 - 44 lead plastic leaded chip carrier, package outline drawing is not to scale. plcc d ne e1 e 1 n d1 nd cp b d2/e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2
m27v160 16/17 table 17. so44 - 44 lead plastic small outline, 525 mils body width, package mechanical data symbol millimeters inches typ min max typ min max a 2.80 0.1102 a1 0.10 0.0039 a2 2.30 2.20 2.40 0.0906 0.0866 0.0945 b 0.40 0.35 0.50 0.0157 0.0138 0.0197 c 0.15 0.10 0.20 0.0059 0.0039 0.0079 cp 0.08 0.0030 e 13.30 13.20 13.50 0.5236 0.5197 0.5315 eh 16.00 15.75 16.25 0.6299 0.6201 0.6398 d 28.20 28.00 28.40 1.1102 1.1024 1.1181 e 1.27 C C 0.0500 C C l 0.80 0.0315 n44 44 a 8 8 figure 14. so44 - 44 lead plastic small outline, 525 mils body width, package outline drawing is not to scale. so-d e n d c l a1 a eh a 1 e cp b a2
17/17 m27v160 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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